1. Field of Invention
The present invention relates to a method for fabricating a DRAM capacitor. More particularly, the present invention relates to a method for fabricating a lower electrode of the capacitor.
2. Description of Related Art
FIGS. 1A to 1C are schematic, cross-sectional diagrams showing the fabrication steps of a lower electrode of a capacitor, while FIGS. 2A to 2C are schematic, cross-sectional diagrams taken at right angle to the first cross-sectional views and bisecting at a line II--II in FIGS. 1A to 1C.
Referring to FIG. 1A and FIG. 2A, a substrate 100 is provided with isolation structures formed therein. A gate 111 is then formed on the substrate 100, wherein the gate 111 is constituted by stacking a gate oxide layer 108, a conducting layer such as a polysilicon layer or a tungsten silicide layer, and a cap layer 112 in sequence on the substrate 100. A spacer 114 is formed on a sidewall of the gate 111 before forming a source/drain (S/D) region by doping in the substrate 100. Landing pads 106a and 106b are formed to couple with the S/D region. A patterned first dielectric layer 102 is formed to cover, a part of the landing pads 106a, 106b, the exposed cap layer 112, and the substrate 100.
Further referring to FIG. 1A and FIG. 2A, a bit line 116 is formed to cover the landing pad 106a and a part of the dielectric layer 102 before forming a second dielectric layer 104 on the first dielectric layer 102. An etching step is performed to form a contact opening 118, which extends through the second dielectric layer 104 and the first dielectric layer 102 to expose the landing pads 106b.
Referring to FIG. 1B and FIG. 2B, a doped polysilicon layer 120 is formed to fill the contact opening 118 and covers the second dielectric layer 104.
Referring to FIG. 1C and FIG. 2C, the doped polysilicon layer 120 is patterned to form a first storage node 120a and a second storage node 120b, which serve as lower electrodes of a capacitor.
The contact opening 118 formed by the conventional process may easily expose the bit line when a misalignment occurs during the contact formation. As a result, a doped polysilicon layer that is subsequently deposited in the contact opening makes contact with the exposed bit line, leading to an electrical short circuit and a damage to the semiconductor device.
With the increased integration for the integrated circuit, the problem mentioned above gets worse as a gap width between the sidewall of the contact opening and the bit line has gradually decreased to, for example about 0.05 microns. One solution for above problem is to increase the gap width between the sidewall of the contact opening and the bit line. An increase in gap width is commonly achieved by decreasing the size of the contact opening. Since the contact opening manufactured by photolithography has a size limitation, only the narrow gap is formed as a consequence. If the gap between the contact and the bit line is too narrow, the doped polysilicon layer that fills the contact opening may form an unnecessary contact with the bit lines when misalignment occurs, leading to the electrical short circuit.
Conventionally, an increase in the storage charge of the capacitor is achieved by increasing the surface area of a lower electrode. So, a thicker doped polysilicon layer is usually formed for manufacturing the lower electrode. As there is a very small gap in between two adjacent capacitors, it is not easy to completely etch through the thicker doped polysilicon layer for separating two adjacent capacitors, due to a large aspect ratio of the thick doped polysilicon layer.